This invention relates generally to signal processing, and more particularly to a method and system for implementing a voltage controlled oscillator (VCO) based analog-to-digital converter (ADC).
An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal that is an approximation of the analog input signal. The resolution of an ADC defines the accuracy of the approximation between the digital output signal and the analog input signal. In this regard, the closer the resemblance between the digital output signal and the analog input signal, the greater the resolution of the ADC. ADCs are well known in the art and they can have various architectures. In general, each ADC architecture has specific characteristics that can make it suitable or unsuitable for a particular application.
One of the most popular ADC architectures is a pipeline ADC. Pipeline ADCs generally find application in systems operating at speeds of 10-200 MHz and requiring moderate resolution on the order of 10-14 bits. Their power consumption can be classified as being moderate when compared to other types of ADCs. A typical architecture of a pipeline ADC can include a plurality of consecutively coupled processing stages that can include a track-and-hold (T/H) circuit, and a summation circuit and amplification circuit coupled to each stage. A major drawback with pipeline ADC""s involves latency occurring at various processing stages. For this and other reasons, pipeline ADCs are extremely sensitive to non-linearities affecting offset and gain.
Another popular ADC architecture is the sigma-delta ADC. The sigma-delta ADC typically finds application in systems processing signals at speeds of less than 20 MHz and requiring high resolution of the order of 12-24 bits. A typical sigma-delta ADC can include a comparator and several integrators having a feedback loop containing a 1-bit DAC. Notwithstanding, although sigma-delta ADCs can provide a higher resolution than pipeline ADCs, their application is limited by their speed.
Another popular ADC architecture is a flash ADC. Although flash ADCs can operate at speeds in excess of 1 GHz, power consumption is extremely high. Furthermore, their cost can be very high when compared to other ADCS.
Given these trade-offs and other inherent drawbacks, there is a need for a method and system for providing a more flexible ADC in terms of operating speed, power consumption, and cost.
The invention provides a method for converting an analog input signal to a digital output signal. The method can include converting the analog input signal to at least one intermediate signal having a frequency dependent on the analog input signal. A frequency of one or more intermediate signals can subsequently be determined. The determined frequency can be mapped to an output value that represents the digital output signal. The converting step can further include the step of converting a voltage of the analog input signal to an intermediate frequency dependent signal. In accordance with the invention, linearity of the digital output signal can be controlled by controlling the conversion of the voltage of the analog input signal to an intermediate frequency dependent signal. Notably, the resolution of the digital output signal can be controlled by controlling the determination of the frequency of one or more of the intermediate signals.
In another aspect of the invention, an analog-to-digital converter is provided. The ADC can be configured to convert an analog input signal to a digital output signal. The ADC can include a voltage controlled oscillator for converting the analog input signal to one or more intermediate signals having a frequency dependent on the magnitude of the analog input signal. At least one frequency detector can be coupled to the VCO for determining the frequency of one or more intermediate signals generated by the VCO. A mapping circuit can be configured to map the frequency of one or more intermediate signals to an output value. The output value can represent the digital output signal representative of the converted analog input signal.
Alternatively, a processor such as a digital signal processor or an FPGA can replace and perform the functions of the frequency detector and mapping circuit. The voltage controlled oscillator can include means for converting a voltage of the analog input signal to the intermediate signal, whose frequency is dependent on the magnitude of the analog input signal. The VCO can further include means for controlling a linearity of the ADC. Notably, the frequency detector can further include means for controlling a resolution of the ADC. One or more of the frequency detectors and the mapping circuit can be embodied in a digital signal processor (DSP) or an FPGA.
In another aspect of the invention, an analog-to-digital converter is provided for converting an analog input signal to a digital output signal. The ADC can include a voltage controlled oscillator for converting the analog input signal to one or more intermediate signals having a frequency dependent on the magnitude of the analog input signal. A processor can be configured to determine the frequency of one or more of the intermediate signals and map the frequency of the intermediate signal or signals to an output value. The output value can be representative of the digital output signal. The processor can be a DSP.
The VCO can include means for converting a voltage of the analog input signal to the intermediate signal, whose frequency is dependent on the voltage of the analog input signal. The VCO can further include means for controlling the linearity of the ADC. The frequency detector can further include means for controlling a resolution of the ADC.
In a further aspect of the invention, an analog-to-digital converter can be provided for converting an analog input signal to a digital output signal. The ADC can include means for converting an analog input signal to one or more intermediate signals having a frequency dependent on the magnitude of the analog input signal. A means can be provided for determining the frequency of one or more of the intermediate signals and for mapping one or more of the intermediate signals to an output value. The output value can be representative of the digital output signal.